inkcenter's repos on GitHub
Verilog · 20 watchers
JPEG2000_serial
JPEG2000 compression coder on Xilinx Virtex 5 FPGA
Python · 1 watchers
AutoVote
Automated scripts for voting on websites, for my cousin sister.
1 watchers
gitignore
A collection of useful .gitignore templates
Python · 1 watchers
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
Python · 1 watchers
PyVerilog-1
Python-based Verilog Parser (currently Netlist only)
Python · 1 watchers
SimpleNetlist
This repository contains a simple model for representing netlist (electronics) in python
Python · 1 watchers
Verilog-Automatic
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
JavaScript · 0 watchers
500lines
500 Lines or Less
Vim script · 0 watchers
Baiyan_Profile
My custom run commands (.*rc) file for bash, vim & etc. from server in Baiyan
SourcePawn · 0 watchers
CP_AutoScr
Automated scripts for my project Calibration Path
Python · 0 watchers
FileSynScript
in order to synchronize the files between several computers
VimL · 0 watchers
molokai
Molokai color scheme for Vim
Python · 0 watchers
netlist_parser.py
A Python based netlist parser, including Verilog and SPICE
Python · 0 watchers
netlist_parser.py-1
A Python based netlist parser, including Verilog and SPICE
Python · 0 watchers
pymtl
Python-based hardware modeling framework
Python · 0 watchers
PySpice
Simulate electronic circuit using Python and the Ngspice / Xyce simulators
VimL · 0 watchers
Vundle.vim
Vundle, the plug-in manager for Vim
Perl · 0 watchers
YaFSM
Yet Another FSM - Perl base code generator (c++) for Finite State Machines